1. Field of the Invention
The present invention relates to a solid state image pickup device including an analog-to-digital (A/D) converting circuit used for an image capturing signal process of a digital camera, a camcorder, an endoscope, or the like.
Priority is claimed on Japanese Patent Application No. 2011-002949, filed Jan. 11, 2011, the content of which is incorporated herein by reference.
2. Description of the Related Art
All patents, patent applications, patent publications, scientific articles, and the like, which will hereinafter be cited or identified in the present application, will hereby be incorporated by reference in their entirety in order to describe more fully the state of the art to which the present invention pertains.
In recent years, solid state image pickup devices such as charge coupled devices (CCDs) image sensor and complementary metal-oxide semiconductor (CMOS) image sensors have been mounted in image pickup devices such as digital cameras, camcorders, endoscopes, and the like. The image pickup devices are commonly used both domestically and abroad, and demands for a further reduction in the size of the image pickup device and low power consumption are increasing.
In order to meet the demands for the size reduction and low power consumption of the solid state image pickup device, for example, Japanese Unexamined Patent Application, First Publication No. 2005-347932 discloses a solid state image pickup device including a plurality of correlated double sampling (CDS) circuits and a plurality of A/D converters. In the solid state image pickup device disclosed in Japanese Unexamined Patent Application, First Publication No. 2005-347932, the CDS circuit and the A/D converter are arranged for each column of pixels arranged in the form of a two-dimensional matrix. Each of the A/D converters receives a voltage output from pixels (hereinafter referred to as a “pixel signal”) via the CDS circuit. The A/D converter obtains a digital image signal having a high signal to noise ratio (SNR) by performing A/D conversion on the input pixel signal.
As the A/D converter mounted in the solid state image pickup device, an A/D converter of a time to digital converter (TDC) type configured by a digital circuit may be used. The A/D converter of the TDC type (hereinafter referred to as an “A/D converting circuit”) outputs a digital image signal A/D-converted from an input pixel signal by outputting a pulse having a frequency corresponding to the input pixel signal and counting the pulse with a counter.
FIG. 7 is a block diagram illustrating a schematic configuration of an A/D converting circuit (an A/D converter of a TDC type). The A/D converting circuit illustrated in FIG. 7 includes a delay circuit 11, a counter 12, a latch circuit 13, and a latch/encoder circuit 14.
The latch circuit 11 includes a plurality of delay elements (one delay element AND1 and a plurality of delay elements DU1 in FIG. 7), which are connected in a ring form. A pixel signal, which is to be subjected to A/D conversion, is input to each of the delay elements in the delay circuit 11 as an input signal Vin. Each of the delay elements in the delay circuit 11 delays an input pulse φPL by a delay time according to a voltage difference between a signal level of the input signal Vin and a ground (GND) level using the input signal Vin as a power voltage. Then, the delay circuit 11 generates a pulse signal φCK having a frequency corresponding to the delay time of each delay element.
The counter 12 counts the pulse signal φCK generated by the delay circuit 11, that is, a circulation number in which the input pulse φPL has circulated the delay circuit 11, and outputs the count result as a digital signal φD1. The latch circuit 13 stores (latches) the digital signal φD1 output from the counter 12, and outputs the latched digital signal as a digital signal φD2. The latch/encoder circuit 14 receives outputs of the delay elements in the delay circuit 11, detects a passing stage number of the delay elements of the delay circuit 11 through which the input pulse φPL has passed, that is, position information of the pulse signal φCK inside the delay circuit 11, and outputs the detection result as a digital signal φD3.
The A/D converting circuit outputs a digital signal φD4 corresponding to the signal level of the input signal Vin, that is, the pixel signal, which includes the digital signal φD2 output from the latch circuit 13 as data of a high-order bit and the digital signal φD3 output from the latch/encoder circuit 14 as data of a low-order bit. The digital signal φD4 serves as a digital image signal (digital value) A/D-converted by the A/D converting circuit.
Here, a description will be made in connection with a solid state image pickup device in which the A/D converting circuit illustrated in FIG. 7 is arranged for each column of pixels arranged in the form of a two-dimensional matrix. FIG. 8 is a block diagram illustrating a schematic configuration of a solid state image pickup device in which an A/D converting circuit (an A/D converter of a TDC type) is arranged for each column of pixels. The solid state image pickup device illustrated in FIG. 8 includes a pixel unit 1 including a plurality of pixels 2 arranged in the form of a matrix, a signal processing unit 3, a vertical driving unit 7, a horizontal driving unit 8, and a control circuit 9. The signal processing unit 3 includes a plurality of CDS circuits 51 to 54 and a plurality of A/D converting circuits 41 to 44.
The A/D converting circuits 41 to 44 include delay circuits 411 to 441 and pulse passing stage number detecting circuits 412 to 442, respectively. Each of the delay circuits 411 to 441 arranged in the A/D converting circuits 41 to 44 has the same configuration as the delay circuit 11 arranged in the A/D converting circuit illustrated in FIG. 7. Each of the pulse passing stage number detecting circuits 412 to 442 includes a circuit having a configuration in which the counter 12, the latch circuit 13, and the latch/encoder circuit 14 of the A/D converting circuit illustrated in FIG. 7 are combined.
When the A/D converting circuit is arranged for each column of the pixel unit as in the solid state image pickup device illustrated in FIG. 8, for example, several hundred to several thousand A/D converting circuits are arranged in a narrow range having a width of several micrometers (μm). In this case, when a GND line is arranged for each A/D converting circuit, an area of the GND line increases. Thus, a common GND line is connected to all of the A/D converting circuits 41 to 44 as in the solid state image pickup device illustrated in FIG. 8. Lines for pixel signals input to the A/D converting circuits 41 to 44 are also arranged to pass through the narrow range having a width of several micrometers (μm).
As described above, the A/D converting circuit outputs the digital signal φD4 corresponding to the circulation number of the input pulse φPL, which circulates during the delay time corresponding to the voltage difference between the signal level of the pixel signal (the input signal Vin) and the GND level, and the passing stage number of the delay element. For this reason, an operation current of the A/D converting circuit changes depending on the signal level of the input signal Vin or impedance of a line. The operation current of the A/D converting circuit also varies in terms of time according to a status in which the input pulse φPL is passing through the plurality of delay elements (the delay element AND1 and the delay elements DU1).
More specifically, a current It1 flowing through the GND line of the delay circuit 411 arranged in the A/D converting circuit 41, a current It2 flowing through the GND line of the delay circuit 421 arranged in the A/D converting circuit 42, a current It3 flowing through the GND line of the delay circuit 431 arranged in the A/D converting circuit 43, and a current It4 flowing through the GND line of the delay circuit 441 arranged in the A/D converting circuit 44 change depending on the signal levels of the input signals input to the delay circuits 411 to 441 and operation statuses of a plurality of delay elements according to the passing of the input pulse φPL. As described above, the current flowing through the GND line connected in common to all columns changes depending on the signal level of the input signal of each row, that is, the signal level of the pixel signal.
A current I1 flowing through an input line from the CDS circuit 51 to the delay circuit 411, a current I2 flowing through an input line from the CDS circuit 52 to the delay circuit 421, a current I3 flowing through an input line from the CDS circuit 53 to the delay circuit 431, and a current I4 flowing through an input line from the CDS circuit 54 to the delay circuit 441 change depending on the signal levels of the input signals input to the delay circuits 411 to 441 and operation statuses of a plurality of delay elements according to the passing of the input pulse φPL.
Due to the change in the current, a voltage of a voltage drop by resistive components of the input lines and the GND line of the A/D converting circuits 41 to 44 changes, and voltage levels of the input and the GND of the delay circuits 441 to 441 change. Due to the change in the input and GND voltages of the delay circuits 411 to 441 and the GND, even though input signals having the same delay time in the delay circuit (for example, the same input signal Vin) are A/D-converted, the A/D converted digital signals φD4 output from the A/D converting circuits 41 to 44 change according to signal levels of pixel signals simultaneously read out and output from pixels 2 of different columns arranged in the same row in the pixel unit 1. For this reason, as illustrated in FIGS. 9A and 9B, the pixels 2 in the pixel unit 1 differ in a digital image signal (a digital value).
FIGS. 9A and 9B are diagrams schematically illustrating an example in which the digital values output from the A/D converters of the TDC type (the A/D converting circuits 41 to 44) vary according to the pixel 2. FIG. 9A is a diagram schematically illustrating an amount of light incident to the pixels 2 arranged in the form of a 4-by-4 matrix in the pixel unit 1. FIG. 9B is a diagram schematically illustrating levels of digital values obtained by A/D converting the pixel signals, corresponding to the amount of incident light, output from the pixels 2 through the A/D converting circuits corresponding to the respective pixel columns. In the following description, the position of each pixel 2 is represented by inputting digits indicating the row number and the column number of the pixel unit 1 to “( ): parentheses” added behind the symbol of the pixel 2. A first digit in “( ): parentheses” represents a row number, and a second digit represents a column number. For example, a pixel 2 at a second row and a third column is represented by a pixel 2(2,3).
FIG. 9A illustrates an aspect in which, as the color of each pixel 2 changes from black to white, the amount of light incident to the pixel 2 increases. FIG. 9B illustrates an aspect in which, as the color corresponding to each pixel 2 changes from black to white, the digital value A/D converted from the pixel signal output from each pixel 2 increases. That is, black represents a status in which the amount of light incident to the pixel 2 is small and the digital value is small, whereas white represents a status in which the amount of light incident to the pixel 2 is large and the digital value is large,
FIG. 9A illustrates a case in which the amount of incident light has two statuses. More specifically, FIG. 9A shows a state in which a pixel 2(1,1), a pixel 2(1,2), a pixel 2(1,3), a pixel 2(2,2), a pixel 2(2,3), and a pixel 2(3,3) are large in the amount of incident light, whereas a pixel 2(1,4), a pixel 2(2,1), a pixel 2(2,4), a pixel 2(3,1), a pixel 2(3,2), a pixel 2(3,4), a pixel 2(4,1), a pixel 2(4,2), a pixel 2(4,3), and a pixel 2(4,4) are small in the amount of incident light.
When the A/D converting circuits corresponding to the respective pixel columns have the same operation current, the digital values having the same tendency as in FIG. 9A are expected to be output. However, actually, the A/D converted digital values have values of different levels due to the change in the operation current of the A/D converting circuit as illustrated in FIG. 9B. For example, as illustrated in FIG. 9A, the pixel 2(3,1) and the pixel 2(3,2) have the same amount of incident light, however, the digital value corresponding to the pixel 2(3,1) is different from the digital value corresponding to the pixel 2(3,2).
As described above, even when the pixels 2 are the same in the amount of incident light and outputs the pixel signals of the same signal level, the levels of the A/D converted digital values change by the signal levels of the pixel signals output from the pixels 2 of different columns arranged in the same row in the pixel unit 1.
In order to cope with the change in the voltage levels of the input and the GND of the delay circuit, Japanese Unexamined Patent Application, First Publication No. 2010-141685 discloses the following technique. In an A/D converting circuit disclosed in Japanese Unexamined Patent Application, First Publication No. 2010-141685, an input signal Vin is first input to a buffer, and a capacitor is connected between an output signal line of the buffer and a GND signal line as illustrated in FIG. 10. An output of the buffer is supplied to delay elements of a delay circuit as a power voltage. This configuration is the same as a configuration in which a bypass capacitor is arranged between the signal line of the input signal Vin and the GND signal line. In a technique disclosed in Japanese Unexamined Patent Application, First Publication No. 2005-347932, the above configuration is employed to suppress a change in voltage levels of the input signal Vin and the GND of the A/D converting circuit.
However, generally, a circuit area necessary for implementing a capacitor in a digital circuit of a CMOS type is very large compared to other digital circuits (for example, the delay element DU1). Thus, a circuit area of the A/D converting circuit having the configuration, illustrated in FIG. 10, disclosed in Japanese Unexamined Patent Application, First Publication No. 2005-347932 also increases. For this reason, when the A/D converting circuit having the configuration disclosed in Japanese Unexamined Patent Application, First Publication No. 2005-347932 is employed as is and mounted for each column of the pixel unit in the solid state image pickup device in which the A/D converting circuit is arranged for each column of the pixel unit as disclosed in Japanese Unexamined Patent Application, First Publication No. 2010-141685, the circuit area of the solid state image pickup device increases, and the size of the solid state image pickup device increases. In particular, in recent solid state image pickup devices, the number of pixels tends to increase. However, if the number of A/D converting circuits mounted for each column of the pixel unit increases with the increase in the number of pixels, it will be difficult to implement the solid state image pickup device in which the A/D converting circuits are mounted.